1. Field of the Invention
The present invention relates generally to semiconductor devices and more specifically to such devices which are adapted to provide signal outputs at high power levels and high frequencies.
2. Description of the Prior Art
Significant advances in modern technology have increased the demand for semiconductor devices which are capable of providing output signals at high power levels, such as 50 watts, and at high frequencies, such as 3 Gigahertz (GHz). This demand has also made it desirable to provide the semiconductor devices with a lower Q which corresponds to a wider bandwidth. The wider bandwidth enables the device to accommodate additional data channels which significantly increases the data throughput of the device.
Furthermore, it is always desirable to decrease in the internal losses of the semiconductor device since any power dissipated in the transistor package itself reduces the total power provided at the output of the device.
The semiconductor devices of the prior art have typically had low output impedances. These devices have commonly been used with transmission line systems and antenna systems which have a nominal impedance of 50 ohms. In order to match a semiconductor device to these systems and minimize the losses associated with the matching, elaborate impedance matching networks have been interposed between the semiconductor device and the associated system. These impedance matching networks increase the output impedance of the semiconductor device to provide an appropriate match with the impedance of the associated system. Typically, the output impedance for a high power semiconductor device is between 1 and 5 ohms. In order to match this impedance to a nominal 50 ohm level, the impedance matching networks have typically increased the output impedance of the device by a factor of 10 to 50.
The use of external impedance matching networks, especially tunable networks, significantly increases the cost of a high frequency amplifier. Also, due to additional components, the overall reliability of the combination is reduced while the size is increased. Impedance matching networks typically used in the above described manner include Chebyshev transformers, quarter wave transformers, L-networks and RLC networks.
Of course it is desirable to provide a semiconductor device with a high output impedance not only to reduce the complexity of the associated impedance matching networks but also to reduce the output current. Lower output currents result in lower power losses within the semiconductor device.
The bandwidth limitation, the internal losses, and the impedance matching characteristics of the semiconductor devices are all related to certain parasitic reactances within the transistor package and also to the lead bonds and parasitics associated with the transistor die. Of particular interest in the present invention are those parasitic reactances which inherently occur in the output of the transistor die and package. These reactances include a shunt capacitance, a virtual resistance, and a series inductance.
The shunt capacitance is associated with the transistor die which has a certain amount of inherent capacitance. This inherent capacitance increases directly with the power and the size of the transistor die.
The virtual resistance is actually located externally of the transistor but is commonly considered inside the transistor package for the purpose of determining optimum collector load impedance. The value of this virtual resistance is related to the collector voltage, the saturation voltage and the power output of the transistor.
The series inductance is an unavoidable package parasitic inductance. This inductance results primarily from the physical length of the collector lead bonds. Of course the collector lead bonds will always have some length so that there will always be some series inductance.
In combination these parasitic quantities result in an equivalent circuit including a relatively low value of series resistance and relatively high value of series reactance. The relatively low value of the series resistance reduces the magnitude of the output impedance so that significant transformations are required by an external matching network.
Of course the lower output impedances of the devices of the prior art provide relatively high output currents. As a consequence, the resistance losses in the transistor package have been relatively high. For example, a typical loss in the parasitic series inductance might be as high as 9% of the total power developed by the transistor.
The theoretical bandwidth of these semiconductor devices is equal to the value of the series resistance divided by the value of the series reactance. Since the value of the series resistance in the devices of the prior art has been relatively low, the theoretical bandwidth of these devices has been relatively narrow.